Digital receivers have become more and more popular in radar, communication, and electric warfare for

the advantages compared with their analog counterparts. But conventional digital receivers have been generally considered impractical for bandwidth greater than several hundreds MHz. To extend receiver bandwidth, decrease data

rate and save hardware resources, three novel structures are proposed. They decimate the data stream prior to mixing and filtering, then process the multiple decimated streams in parallel at a lower rate. Consequently it is feasible

to realize wideband receivers on the current ASIC devices. A design example and corresponding simulation results

are demonstrated to evaluate the proposed structures.

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