Journal of Systems Engineering and Electronics ›› 2012, Vol. 23 ›› Issue (2): 179-187.doi: 10.1109/JSEE.2012.00023

• ELECTRONICS TECHNOLOGY • Previous Articles     Next Articles

Efficient multiuser detector based on box-constrained deregularization and its FPGA design

Zhi Quan1,2,* and Jie Liu3   

  1. 1. Department of Electrical Engineering, Federal University of Juiz de Fora, Juiz de Fora 36036900, Brazil;
    2. School of Information Engineering, Department of Electronic Information Engineering, Zhengzhou University,
        Zhengzhou 450001, P. R. China;
    3. RF Engines Limited, Newport PO30 5WB, UK
  • Online:2012-04-20 Published:2010-01-03

Abstract:

Multiuser detection can be described as a quadratic optimization problem with binary constraint. Many techniques are available to find approximate solution to this problem. These techniques can be characterized in terms of complexity and detection performance. The “efficient frontier” of known techniques include the decision-feedback, branch-and-bound and probabilistic data association detectors. The presented iterative multiuser detection technique is based on joint deregularized and box-constrained solution to quadratic optimization with iterations similar to that used in the nonstationary Tikhonov iterated algorithm. The deregularization maximizes the energy of the solution, this is opposite to the Tikhonov regularization where the energy is minimized. However, combined with box-constraints, the deregularization forces the solution to be close to the binary set. We further exploit the boxconstrained dichotomous coordinate descent (DCD) algorithm and adapt it to the nonstationary iterative Tikhonov regularization to present an efficient detector. As a result, the worst-case and average complexity are reduced down to K2.8 and K2.5 floating point operation per second, respectively. The development improves the “efficient frontier” in multiuser detection, which is illustrated by simulation results. Finally, a field programmable gate array (FPGA) design of the detector is presented. The detection performance obtained from the fixed-point FPGA implementation shows a good match to the floating-point implementation.