Journal of Systems Engineering and Electronics ›› 2018, Vol. 29 ›› Issue (6): 1136-1141.doi: 10.21629/JSEE.2018.06.03

• Electronics Technology • Previous Articles     Next Articles

FPGA-based high resolution DPWM control circuit

Hu SONG1,2(), Naiti JIANG2(), Shanshan HU1(), Hongtao LI1,*()   

  1. 1 School of Electronic and Optical Engineering, Nanjing University of Science and Technology, Nanjing 210094, China
    2 Nanjing Marine Radar Institute, Nanjing 210003, China
  • Received:2017-11-06 Online:2018-12-25 Published:2018-12-26
  • Contact: Hongtao LI E-mail:songh_ee@163.com;Jnt724@126.com;787095030@qq.com;liht@njust.edu.cn
  • About author:SONG Hu was born in 1980. He received his master degree in mechanical engineering from Nanjing University of Science and Technology in 2005. After that, he joined Nanjing Marine Radar Institute and worked as a system engineer. He is now a Ph.D. candidate in Nanjing University of Science and Technology. His research interests are radar system and high speed signal processing, with an emphasis on broadband array signal processing. E-mail: songh_ee@163.com|JIANG Naiti was born in 1984. He received his master degree in electronic engineering from Nanjing University of Information Engineering in 2010. He joined Nanjing Marine Radar Institute since 2010. He is now a Ph.D. student in Nanjing University of Information Science and Technology. His research interests are signal processing and data processing of marine radar system. E-mail:Jnt724@126.com|HU Shanshan was born in 1992. She received her master degree in electronic engineering from Nanjing University of Science and Technology in 2017. She joined Nanjing Metro company since 2017. She is a graduate student in Nanjing University of Science and Technology. Her research interest is radar signal processing. E-mail: 787095030@qq.com|LI Hongtao was born in 1979. He received his Ph.D. degree in electronic engineering from Nanjing University of Science and Technology in 2012. He is now an associate professor in School of Electronic and Optical Engineering, Nanjing University of Science and Technology. His research interests are array signal processing and FPGA high speed design. E-mail: liht@njust.edu.cn
  • Supported by:
    the National Natural Science Foundation of China(61401204);the Fundamental Research Funds for the Central Universities(30916011319);the Technology Research and Development Program of Jiangsu Province(BY2015004-03);the Postdoctoral Science Foundation of Jiangsu Province(1501104C);This work was supported by the National Natural Science Foundation of China (61401204), the Fundamental Research Funds for the Central Universities (30916011319), the Technology Research and Development Program of Jiangsu Province (BY2015004-03), and the Postdoctoral Science Foundation of Jiangsu Province (1501104C)

Abstract:

Two improved structures of high resolution digital pulse width modulator (DPWM) control circuit are proposed. Embedded digital clock manager (DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array (FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides, the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.

Key words: digital clock manager (DCM), digital programmable delay circuit, digital pulse width modulator (DPWM)