Journal of Systems Engineering and Electronics ›› 2010, Vol. 21 ›› Issue (1): 20-26.doi: 10.3969/j.issn.1004-4132.2010.01.004

• ELECTRONICS TECHNOLOGY • Previous Articles     Next Articles

Design and realization of synchronization circuit for GPS software receiver based on FPGA

Xiaolei Yu1,2,∗, Yongrong Sun1, Jianye Liu1, and Jianfeng Miao1,3   

  1. 1. Navigation Research Center, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, P. R. China;
    2. Faculty of Science and Technology, Deakin University, Geelong VIC 3217, Australia;
    3. Department of Land Surveying & Geo-Informatics, Hong Kong Polytechnic University, Hong Kong, P. R. China
  • Online:2010-02-26 Published:2010-01-03
  • Supported by:

    This work was supported in part by the National High Technology Research and Development Program of China (863 Program) (2006AA12A108) and CSC International Scholarship (2008104769).


With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate array (FPGA), and a series of experiment is done on the hardware platform. The result shows the all-digital synchronization and demodulation of GPS intermediate frequency (IF) signal can be realized and applied in
embedded real-time GPS software receiver system. It is verified that the decision-directed joint tracking algorithm of carrier phase and symbol timing for received signals from GPS is reasonable. In addition, the loop works steadily and can be used for receiving GPS signals using synchronous demodulation. The synchronization
circuit for GPS software receiver designed based on FPGA has the features of low cost, miniaturization, low power and realtime. Surely, it will become one of the development directions for GPS and even GNSS embedded real-time software receiver.