Abstract:

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed. The validity of this method is proven theoretically. Specifically, testcases are generated according to many approaches of randomization. Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language. Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily. The comparison method is put to use in the evaluation approach of the testing validity. The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing. The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.